io - How do Intel CPUs that use the ring bus topology decode and handle port I/O operations - Stack Overflow
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PCI Express bridging: Optimizing PCI read performance - Embedded Computing Design
System address map initialization in x86/x64 architecture part 2: PCI express-based systems | Infosec Resources
Down to the TLP: How PCI express devices talk (Part I) | xillybus.com
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DMA buffers
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Exploring The Host Memory Buffer Feature - The Toshiba RC100 SSD Review: Tiny Drive In A Big Market
System address map initialization in x86/x64 architecture part 2: PCI express-based systems | Infosec Resources
Buffer Memory - an overview | ScienceDirect Topics
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Bus Specifics - Writing Device Drivers
PCIe
